1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a chip scale package (CSP) structure and to a semiconductor device manufactured by the method.
2. Description of the Related Art
Although bare chip mounting is ideal for high-density mounting of a semiconductor device, it is difficult to guarantee the quality of bare chips and to handle them. Consequently, CSPs having a size near to that of a chip have been developed. In recent years, higher-density mounting has been desired because of the need for further reducing the size of electronic equipment, thus technologies in which passive devices that have been mounted around a CSP on a substrate are packaged in the CSP have been developed. Methods for containing capacitors in a CSP include a method for manufacturing a semiconductor device that has a semiconductor substrate having a circuit-element formation area and a plurality of connection pads formed thereon, an insulation film formed on the circuit-element formation area, and a plurality of columnar electrodes connected to the connection pads (for example, Patent Document 1). The method includes a step of forming a first conductive layer on the circuit-element formation area on the semiconductor substrate through the insulating film sandwiched therebetween and a step of forming a dielectric layer on the first conductive layer and forming a second conductive layer on the dielectric layer to form a capacitive element.
Methods for containing inductors in a CSP include a method for manufacturing a semiconductor device that has a semiconductor substrate having a circuit-element formation area and a plurality of connection pads formed thereon, an insulation film formed on the circuit-element formation area, a plurality of first conductive layers that are connected to the connection pads and are provided on the circuit-element formation area through the insulation film sandwiched therebetween, and a plurality of columnar electrodes provided on the first conductive layers (for example, Patent Document 2). The method includes a step of forming at least one second conductive layer over the insulating film and a step of forming an inductive element from the second conductive layer.
Patent Document 1 Japanese Unexamined Patent Application Publication No. 2002-57291
Patent Document 2 Japanese Unexamined Patent Application Publication No. 2002-57292
However, sputtering, photolithography, and electroplating are used for forming passive devices in the known technologies described above, thus disadvantageously having the increased number of required processes and therefore raising its cost.